Allwinner /D1H /UART[0] /LCR

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Interpret as LCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (five)dls0 (one)stop 0 (disabled)pen 0 (odd)eps0 (bc)bc 0 (rx_buffer)dlab

pen=disabled, stop=one, eps=odd, dlab=rx_buffer, dls=five

Description

UART Line Control Register

Fields

dls

Data Length Select

0 (five): 5 bits

1 (six): 6 bits

2 (seven): 7 bits

3 (eight): 8 bits

stop

Number of stop bits

0 (one): 1 stop bit

1 (two): 1.5 stop bits when DLS(LCR[1:0]) is zero, else 2 stop bits

pen

Parity Enable

0 (disabled): undefined

1 (enabled): undefined

eps

Even Parity Select

0 (odd): undefined

1 (even): undefined

2 (rs485_data): undefined

3 (rs485_addr): undefined

bc

Break Control Bit

dlab

Divisor Latch Access Bit

0 (rx_buffer): undefined

1 (divisor_latch): undefined

Links

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